 
module top(
  input clk_50M,
  input reset,
  output [4:0] led,
 
//  5V
//GND
output uart_txd,
input  uart_rxd,
//sdcard
input   spi_MISO,
output  spi_MOSI,
output  spi_SCLK,
output  spi_CS,

output                   mem_odt,
output                   mem_cs_n,
output                   mem_cke,
output           [13:0]  mem_addr,
output           [2:0]   mem_ba,
output                   mem_ras_n,
output                   mem_cas_n,
output                   mem_we_n,
output           [3:0]   mem_dm,
inout                    mem_clk,
inout                    mem_clk_n,
inout           [31:0]   mem_dq,
inout           [3:0]    mem_dqs,

input        USB3_UART_IN,
output       USB3_RST_OUT,
output       USB3_PCLK,
inout [31:0] USB3_DQ,
output [1:0] USB3_A,
output       USB3_SLCS_N,
output       USB3_SLWR_N,
output       USB3_SLOE_N,
output       USB3_SLRD_N,
output       USB3_PKTEND_N,
input        USB3_FLAGA,
input        USB3_FLAGB,
input        USB3_FLAGC,
input        USB3_FLAGD,//USB3_CMD_CS
input        USB3_CMD_CLK,
input        USB3_CMD_DAT_U2F,
output       USB3_CMD_DAT_F2U,


  input flash_miso,
  output flash_mosi,
  output flash_cs,
  output flash_clk,


  output video_hs,
  output video_vs,
  output [15:0] video,
  
  input dummy
);

wire myuart_rxd = uart_rxd;
wire myuart_txd;

assign uart_txd = USB3_UART_IN && myuart_txd;


reg sys_rst_n ;// && locked_sdram && locked_cpu && locked_vga;
reg [20:0] reset_delay;
always @(posedge clk_50M or negedge reset) begin
  if (!reset) begin
    reset_delay <= 0;
     sys_rst_n <= 0;
  end else begin
    reset_delay <= reset_delay+1'b1;
     if(reset_delay[20])begin
        sys_rst_n <= 1;
     end
  end
end


assign led[0] = flg;
assign led[1] = flg2;
assign led[2] = 1;
assign led[3] = 1;
assign led[4] = video_busy;

reg [31:0] cnt;
reg flg;
always @(posedge clk_50M or negedge sys_rst_n) begin
  if (!sys_rst_n) begin
    cnt <= 0;
    flg <= 1;
  end else begin
    cnt <= cnt+1'b1;
     if(cnt==32'd50000000)begin
        cnt <= 0;
        flg <= ~flg;
     end
  end
end

reg [31:0] cnt2;
reg flg2;
always @(posedge mem_clk or negedge sys_rst_n) begin
  if (!sys_rst_n) begin
    cnt2 <= 0;
    flg2 <= 1;
  end else begin
    cnt2 <= cnt2+1'b1;
     if(cnt2==32'd50000000)begin
        cnt2 <= 0;
        flg2 <= ~flg2;
     end
  end
end






  wire             ctl_clk;
  wire    [ 13: 0] afi_addr;
  wire    [  2: 0] afi_ba;
  wire             afi_cas_n;
  wire             afi_ras_n;
  wire             afi_cs_n;
  wire             afi_we_n;
  wire             afi_rst_n;

  wire             afi_cke;
  wire             afi_ctl_long_idle;
  wire             afi_ctl_refresh_done;

  wire             afi_odt;
  wire    [  3: 0] afi_rdata_en;
  wire    [  3: 0] afi_rdata_en_full;
  wire             afi_cal_fail;
  wire             afi_cal_success;
  wire             afi_mem_clk_disable;

  wire             ctl_reset_n;




wire local_init_done = afi_cal_success;

localparam CFG_MEM_IF_CS_WIDTH = 1;
localparam CFG_AFI_INTF_PHASE_NUM = 2;
localparam CFG_MEM_IF_BA_WIDTH = 3;
localparam CFG_MEM_IF_ROW_WIDTH = 14;
localparam CFG_MEM_IF_COL_WIDTH = 10;
localparam CFG_INT_SIZE_WIDTH = 4;

wire [CFG_MEM_IF_ROW_WIDTH - 1 : 0]   seq_ac_addr;//14
wire [CFG_MEM_IF_BA_WIDTH - 1 : 0]    seq_ac_ba; //3
wire                                  seq_ac_cas_n;//8
wire                                  seq_ac_ras_n;
wire                                  seq_ac_we_n;
wire                                  seq_ac_cke;
wire                                  seq_ac_cs_n;
wire                                  seq_ac_odt;
wire                                  seq_ac_rst_n;
wire                                  seq_ac_sel;

// wire [31:0] data = {
// seq_ac_addr,
// seq_ac_ba,
// seq_ac_cas_n,
// seq_ac_ras_n,
// seq_ac_we_n,
// seq_ac_cke,
// seq_ac_cs_n,
// seq_ac_odt,
// seq_ac_rst_n,
// seq_ac_sel,
// };

// altsource_probe	probe1 (
//       .probe (count1),
//       .source ()
//       );
// defparam
//   probe1.enable_metastability = "NO",
//   probe1.instance_id = "1111",
//   probe1.probe_width = 32,
//   probe1.sld_auto_instance_index = "YES",
//   probe1.sld_instance_index = 1,
//   probe1.source_initial_value = " 0",
//   probe1.source_width = 32;


// altsource_probe	probe2 (
//       .probe (count2),
//       .source ()
//       );
// defparam
//   probe2.enable_metastability = "NO",
//   probe2.instance_id = "2222",
//   probe2.probe_width = 32,
//   probe2.sld_auto_instance_index = "YES",
//   probe2.sld_instance_index = 1,
//   probe2.source_initial_value = " 0",
//   probe2.source_width = 32;

// altsource_probe	probe3 (
//       .probe (count3),
//       .source ()
//       );
// defparam
//   probe3.enable_metastability = "NO",
//   probe3.instance_id = "3333",
//   probe3.probe_width = 32,
//   probe3.sld_auto_instance_index = "YES",
//   probe3.sld_instance_index = 1,
//   probe3.source_initial_value = " 0",
//   probe3.source_width = 32;


// wire [31:0] addr;
// wire [63:0] data64;

// altsyncram recorder (
//   .clock0 (ctl_clk),
//   .address_a (count3),
//   .data_a ({data_write, count_write}),
//   .wren_a (write),
//   .q_a (),
  
//   .clock1 (clk_50M),
//   .address_b (addr),
//   .data_b (),
//   .wren_b (0),
//   .q_b (data64),
  
//   .aclr0 (1'b0),
//   .aclr1 (1'b0),
//   .addressstall_a (1'b0),
//   .addressstall_b (1'b0),
//   .clocken0 (1'b1),
//   .clocken1 (1'b1),
//   .clocken2 (1'b1),
//   .clocken3 (1'b1),
//   .eccstatus (),
//   .rden_a (1'b1),
//   .rden_b (1'b1));
// defparam
//   recorder.address_reg_b = "CLOCK1",
//   recorder.clock_enable_input_a = "BYPASS",
//   recorder.clock_enable_input_b = "BYPASS",
//   recorder.clock_enable_output_a = "BYPASS",
//   recorder.clock_enable_output_b = "BYPASS",
//   recorder.indata_reg_b = "CLOCK1",
//   recorder.intended_device_family = "Cyclone IV E",
//   recorder.lpm_type = "altsyncram",
//   recorder.operation_mode = "BIDIR_DUAL_PORT",
//   recorder.outdata_aclr_a = "NONE",
//   recorder.outdata_aclr_b = "NONE",
//   recorder.outdata_reg_a = "UNREGISTERED",
//   recorder.outdata_reg_b = "UNREGISTERED",
//   recorder.power_up_uninitialized = "FALSE",
//   recorder.ram_block_type = "M9K",
//   recorder.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
//   recorder.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
//   recorder.numwords_a = 128,
//   recorder.numwords_b = 128,
//   recorder.widthad_a = 7,
//   recorder.widthad_b = 7,
//   recorder.width_a = 64,
//   recorder.width_b = 64,
//   recorder.width_byteena_a = 1,
//   recorder.width_byteena_b = 1,
//   recorder.wrcontrol_wraddress_reg_b = "CLOCK1";

// reg [31:0] data_write;
// reg [31:0] count_write;
// reg [31:0] count1;
// reg [31:0] count2;
// reg [31:0] count3;
// reg seq_ac_sel_dly;
// reg [31:0] data_old;
// reg write;
// always @(posedge ctl_clk or negedge sys_rst_n) begin
//   if (!sys_rst_n) begin
//     count1 <= 0;
//     count2 <= 0;
//     count3 <= 0;
//     data_write <= 0;
//     count_write <= 0;
//     seq_ac_sel_dly <= 0;
//     data_old <= 0;
//     write <= 0;
//   end else begin
//     seq_ac_sel_dly <= seq_ac_sel;
//     write <= 0;
//     if(seq_ac_sel)begin
//       count1 <= count1+1'b1;
//       if(data_old != data)begin
//         data_old <= data;
//         count3 <= count3 + 1'b1;
//         count1 <= 0;
//         data_write <= data;
//         count_write <= count1;
//         write <= 1;
//       end


//     end
//     if(seq_ac_sel!=seq_ac_sel_dly)begin
//       count2 <= count2+1'b1;
//     end
//   end
// end




wire [(CFG_MEM_IF_CS_WIDTH)  - 1 : 0] bg_to_chipsel;
wire [(1                  )  - 1 : 0] bg_to_chip;
wire [(CFG_MEM_IF_BA_WIDTH)  - 1 : 0] bg_to_bank;
wire [(CFG_MEM_IF_ROW_WIDTH) - 1 : 0] bg_to_row;
wire [(CFG_MEM_IF_COL_WIDTH) - 1 : 0] bg_to_col;

wire [CFG_MEM_IF_CS_WIDTH    - 1 : 0] cmd_gen_chipsel;
wire [CFG_MEM_IF_BA_WIDTH    - 1 : 0] cmd_gen_bank;
wire [CFG_MEM_IF_ROW_WIDTH   - 1 : 0] cmd_gen_row;
wire [CFG_MEM_IF_COL_WIDTH   - 1 : 0] cmd_gen_col;
wire do_refresh;
wire my_do_activate;
wire my_do_write;
wire my_do_read;
wire my_do_auto_precharge;
wire my_do_precharge;

assign bg_to_chipsel = cmd_gen_chipsel;
assign bg_to_chip = 1'b1;
assign bg_to_bank = cmd_gen_bank;
assign bg_to_row = cmd_gen_row;
assign bg_to_col = cmd_gen_col;


alt_mem_ddrx_addr_cmd  # (
    .CFG_PORT_WIDTH_TYPE                ( 3                     ),
    .CFG_PORT_WIDTH_OUTPUT_REGD         ( 2              ),
    .CFG_MEM_IF_CHIP                    ( 1                         ),
    .CFG_MEM_IF_CKE_WIDTH           (1           ),
    .CFG_MEM_IF_ADDR_WIDTH          (14       ),
    .CFG_MEM_IF_ROW_WIDTH               ( CFG_MEM_IF_ROW_WIDTH                    ),
    .CFG_MEM_IF_COL_WIDTH               ( CFG_MEM_IF_COL_WIDTH                    ),
    .CFG_MEM_IF_BA_WIDTH                ( CFG_MEM_IF_BA_WIDTH                     ),
    .CFG_DWIDTH_RATIO                   ( 2                     )
) alt_mem_ddrx_addr_cmd_inst (
    .ctl_clk                            ( ctl_clk                                 ),
    .ctl_reset_n                        ( ctl_reset_n                             ),
    .ctl_cal_success                    ( afi_cal_success                         ),
    .cfg_type                           ( 'b001                                ),
    .bg_do_write                        ( my_do_write                  ),
    .bg_do_read                         ( my_do_read                   ),
    .bg_do_auto_precharge               ( my_do_auto_precharge         ),
    .bg_do_activate                     ( my_do_activate               ),
    .bg_do_precharge                    ( my_do_precharge              ),
    .bg_do_refresh                      ( do_refresh                ),
    
    .bg_to_chip                         ( bg_to_chip                   ),
    .bg_to_bank                         ( bg_to_bank                   ),
    .bg_to_row                          ( bg_to_row                    ),
    .bg_to_col                          ( bg_to_col                    ),

    .afi_cke                            ( afi_cke                 ),
    .afi_cs_n                           ( afi_cs_n                ),
    .afi_ras_n                          ( afi_ras_n               ),
    .afi_cas_n                          ( afi_cas_n               ),
    .afi_we_n                           ( afi_we_n                ),
    .afi_ba                             ( afi_ba                  ),
    .afi_addr                           ( afi_addr                ),
    .afi_rst_n                          ( afi_rst_n               )
);

alt_mem_ddrx_odt_gen #
(
    .CFG_DWIDTH_RATIO               (2               ),
    .CFG_ODT_ENABLED                (1                ),
    .CFG_MEM_IF_CHIP                (1                ),
    .CFG_MEM_IF_ODT_WIDTH           (1           ),
    .CFG_PORT_WIDTH_CAS_WR_LAT      (4      ),
    .CFG_PORT_WIDTH_TCL             (4             ),
    .CFG_PORT_WIDTH_ADD_LAT         (4         ),
    .CFG_PORT_WIDTH_TYPE            (3            ),
    .CFG_PORT_WIDTH_WRITE_ODT_CHIP  (1  ),
    .CFG_PORT_WIDTH_READ_ODT_CHIP   (1   ),
    .CFG_PORT_WIDTH_OUTPUT_REGD     (2     )
)
odt_gen_inst
(
    .ctl_clk                        (ctl_clk                        ),
    .ctl_reset_n                    (ctl_reset_n                    ),
    .cfg_type                       ('b001                       ),
    .cfg_tcl                        (5                        ),
    .cfg_add_lat                    (0                    ),
    .cfg_write_odt_chip             (1             ),
    .cfg_read_odt_chip              (0              ),
    .cfg_burst_length               ('b00100               ),
    .bg_do_read                     (bg_do_read          ),
    .bg_do_write                    (bg_do_write         ),
    .bg_to_chip                     (bg_to_chip          ),
    .afi_odt                        (afi_odt         )
);





wire  [  7: 0] afi_dm;
wire  [ 63: 0] afi_wdata;// = sdram_din;
wire [31:0] dio_rdata;
wire [63:0] dio_rdata64;
wire           afi_dqs_burst;
wire           afi_wdata_valid;
wire measure_clk_2x;

	ddr2_phy_alt_mem_phy	ddr2_phy_alt_mem_phy_inst(
		.pll_ref_clk(clk_50M),
		.global_reset_n(sys_rst_n),
		.soft_reset_n(sys_rst_n),

    .reset_request_n(),

		.ctl_clk(ctl_clk),
		.ctl_reset_n(ctl_reset_n),

		.ctl_dm         (afi_dm),
		.ctl_wdata      (afi_wdata),
		.ctl_dqs_burst  (afi_dqs_burst),
		.ctl_wdata_valid(afi_wdata_valid),

    .dio_rdata(dio_rdata),
    .dio_rdata64(dio_rdata64),


		.ctl_addr(afi_addr),
		.ctl_ba(afi_ba),
		.ctl_cas_n(afi_cas_n),
		.ctl_cke(afi_cke),
		.ctl_cs_n(afi_cs_n),
		.ctl_odt(afi_odt),
		.ctl_ras_n(afi_ras_n),
		.ctl_we_n(afi_we_n),
		.ctl_rst_n(afi_rst_n),
		.ctl_mem_clk_disable(afi_mem_clk_disable),

		.ctl_doing_rd(afi_rdata_en),

		.ctl_cal_success(afi_cal_success),
		.ctl_cal_fail(afi_cal_fail),
		.ctl_cal_warning(),

    .measure_clk_2x(measure_clk_2x),

		.mem_addr(mem_addr),
		.mem_ba(mem_ba),
		.mem_cas_n(mem_cas_n),
		.mem_cke(mem_cke),
		.mem_cs_n(mem_cs_n),
		.mem_dm(mem_dm),
		.mem_odt(mem_odt),
		.mem_ras_n(mem_ras_n),
		.mem_we_n(mem_we_n),
		.mem_reset_n(mem_reset_n),
		.mem_clk(mem_clk),
		.mem_clk_n(mem_clk_n),
		.mem_dq(mem_dq),
		.mem_dqs(mem_dqs),
		.mem_dqs_n(mem_dqs_n),

    .seq_ac_addr                        (seq_ac_addr),
    .seq_ac_ba                          (seq_ac_ba),
    .seq_ac_cas_n                       (seq_ac_cas_n),
    .seq_ac_ras_n                       (seq_ac_ras_n),
    .seq_ac_we_n                        (seq_ac_we_n),
    .seq_ac_cke                         (seq_ac_cke),
    .seq_ac_cs_n                        (seq_ac_cs_n),
    .seq_ac_odt                         (seq_ac_odt),
    .seq_ac_rst_n                       (seq_ac_rst_n),
    .seq_ac_sel                         (seq_ac_sel)

    );

	defparam
		ddr2_phy_alt_mem_phy_inst.MEM_IF_MEMTYPE = "DDR2",
		ddr2_phy_alt_mem_phy_inst.DLL_DELAY_BUFFER_MODE = "LOW",
		ddr2_phy_alt_mem_phy_inst.DLL_DELAY_CHAIN_LENGTH = 12,
		ddr2_phy_alt_mem_phy_inst.DQS_DELAY_CTL_WIDTH = 6,
		ddr2_phy_alt_mem_phy_inst.DQS_OUT_MODE = "DELAY_CHAIN2",
		ddr2_phy_alt_mem_phy_inst.DQS_PHASE = 6000,
		ddr2_phy_alt_mem_phy_inst.DWIDTH_RATIO = 2,
		ddr2_phy_alt_mem_phy_inst.MEM_IF_DWIDTH = 32,
		ddr2_phy_alt_mem_phy_inst.MEM_IF_ADDR_WIDTH = 14,
		ddr2_phy_alt_mem_phy_inst.MEM_IF_BANKADDR_WIDTH = 3,
		ddr2_phy_alt_mem_phy_inst.MEM_IF_CS_WIDTH = 1,
		ddr2_phy_alt_mem_phy_inst.MEM_IF_CS_PER_RANK = 1,
		ddr2_phy_alt_mem_phy_inst.MEM_IF_DM_WIDTH = 4,
		ddr2_phy_alt_mem_phy_inst.MEM_IF_DM_PINS_EN = 1,
		ddr2_phy_alt_mem_phy_inst.MEM_IF_DQ_PER_DQS = 8,
		ddr2_phy_alt_mem_phy_inst.MEM_IF_DQS_WIDTH = 4,
		ddr2_phy_alt_mem_phy_inst.MEM_IF_OCT_EN = 0,
		ddr2_phy_alt_mem_phy_inst.MEM_IF_CLK_PAIR_COUNT = 1,
		ddr2_phy_alt_mem_phy_inst.MEM_IF_CLK_PS = 8000,
		ddr2_phy_alt_mem_phy_inst.MEM_IF_CLK_PS_STR = "8000 ps",
		ddr2_phy_alt_mem_phy_inst.PLL_STEPS_PER_CYCLE = 80,
		ddr2_phy_alt_mem_phy_inst.SCAN_CLK_DIVIDE_BY = 2,
		ddr2_phy_alt_mem_phy_inst.MEM_IF_DQSN_EN = 0,
		ddr2_phy_alt_mem_phy_inst.DLL_EXPORT_IMPORT = "EXPORT",
		ddr2_phy_alt_mem_phy_inst.MEM_IF_ADDR_CMD_PHASE = 90,
		ddr2_phy_alt_mem_phy_inst.RANK_HAS_ADDR_SWAP = 0;


wire usb_clk;// usb_clk_out 的话，pc2fpga 少等一个周期，          rd <= 1;          ft_status <= 3;      usb3_cnt==usb3_cnt_max-1
assign USB3_PCLK = usb_clk;
pll_usb pll_usb_inst(
  .areset  (~reset),
  .inclk0             (clk_50M),
  .c0                 (usb_clk),
  .c1                 (usb_clk_out),
  .locked             ()
);


  
//assign K22 = vga_hs ^ vga_vs ^ (video_de ? 0 : (|vga_rgb)) ^ audio_pwm;
assign video_hs = vga_hs;
assign video_vs = vga_vs;
assign video = video_de ? vga_rgb: 0;

wire vga_hs;
wire vga_vs;
wire [15:0] vga_rgb;
wire video_de;


wire sdram_idle;
wire sdram_rw_req;
wire sdram_rw_ack;
wire sdram_read_or_write;
wire [31:0] sdram_rw_addr;
wire [ 8:0] sdram_rw_burst;
wire [31:0] sdram_din;
wire [31:0] sdram_dout;
wire [3:0]  sdram_mask;


wire sdram_clk = ctl_clk;
wire sdram_clk_2x = measure_clk_2x;


wire cpu_clk;
wire vga_clk_65M;

cpu_pll cpu_pll_inst(
  .areset	(~reset),
  .inclk0             (clk_50M),
  .c0                 (cpu_clk),
  .c1                 (),
  .locked             ()
);
 
pll_vga pll_vga_inst(
  .areset	(~reset),
  .inclk0             (clk_50M),
  .c0                 (vga_clk_65M),
  .c1                 (),
  .locked             ()
);
 

wire [7:0] ch375_d = 0;
wire video_busy;
system 
#(
  .H_SYNC(11'd136), //行同步
  .H_BACK(11'd160), //行显示后沿
  .H_DISP(11'd1024),//行有效数据
  .H_TOTAL(11'd1344),  //行扫描周期 
  .V_SYNC(11'd6),  //场同步
  .V_BACK(11'd29),  //场显示后沿
  .V_DISP(11'd768),  //场有效数据
  .V_TOTAL(11'd806),  //场扫描周期
  .EXTRA_UP(11'd0),
  .EXTRA_DOWN(11'd0),
  .SPI_QUARD(0)
)system_inst(
  .clk      (cpu_clk),        //     clk_cpu
	.clk_50M  (clk_50M),
  .sdram_clk(sdram_clk),
`ifdef USE_HALF_DDR
  .sdram_clk_trans(sdram_clk),
`else
  .sdram_clk_trans(sdram_clk_2x),
`endif
  .video_clk (vga_clk_65M),
  .reset_n  (reset),  //   reset.reset_n


  .cmd_gen_chipsel       (cmd_gen_chipsel      ),
  .cmd_gen_bank          (cmd_gen_bank         ),
  .cmd_gen_row           (cmd_gen_row          ),
  .cmd_gen_col           (cmd_gen_col          ),
  .do_refresh            (do_refresh           ),
  .my_do_activate        (my_do_activate       ),
  .my_do_write           (my_do_write          ),
  .my_do_read            (my_do_read           ),
  .my_do_auto_precharge  (my_do_auto_precharge ),
  .my_do_precharge       (my_do_precharge      ),
  .dio_rdata             (dio_rdata            ),
  .dio_rdata64           (dio_rdata64          ),
  .afi_dm                (afi_dm               ),
  .afi_dqs_burst         (afi_dqs_burst        ),
  .afi_wdata             (afi_wdata            ),
  .afi_wdata_valid       (afi_wdata_valid      ),
  .local_init_done       (local_init_done      ),


  .myuart_rxd     (myuart_rxd),     //  myuart.rxd
  .myuart_txd     (myuart_txd),      //        .txd

  .hid_clk   (hid_clk ),
  .hid_dat   (hid_dat ),
  .hid_str   (hid_str ),

  //sdcard
  .softspi_MISO        (spi_MISO),        //     spi.MISO
  .softspi_MOSI        (spi_MOSI),        //        .MOSI
  .softspi_SCLK        (spi_SCLK),        //        .SCLK
  .softspi_CS          (spi_CS),         //        .SS_n    
  

  .USB3_UART_IN    (USB3_UART_IN    ),
  .USB3_RST_OUT    (USB3_RST_OUT    ),
  .USB3_PCLK       (usb_clk         ),
  .USB3_DQ         (USB3_DQ         ),
  .USB3_A          (USB3_A          ),
  .USB3_SLCS_N     (USB3_SLCS_N     ),
  .USB3_SLWR_N     (USB3_SLWR_N     ),
  .USB3_SLOE_N     (USB3_SLOE_N     ),
  .USB3_SLRD_N     (USB3_SLRD_N     ),
  .USB3_PKTEND_N   (USB3_PKTEND_N   ),
  .USB3_FLAGA      (USB3_FLAGA      ),
  .USB3_FLAGB      (USB3_FLAGB      ),
  .USB3_FLAGC      (USB3_FLAGC      ),
  .USB3_FLAGD      (USB3_FLAGD      ),
  .USB3_CMD_CLK    (USB3_CMD_CLK    ),
  .USB3_CMD_DAT_U2F(USB3_CMD_DAT_U2F),
  .USB3_CMD_DAT_F2U(USB3_CMD_DAT_F2U),
  .addr(addr),
  .data64(data64),


  .audio_pwm (audio_pwm),
  
  .ch375_d      (ch375_d  ),
  .ch375_int    (ch375_int),
  .ch375_a0     (ch375_a0 ),
  .ch375_cs_out (ch375_cs ),
  .ch375_rd     (ch375_rd ),
  .ch375_wr     (ch375_wr ),


  //.w25q64_ncs       (w25q64_ncs      ),
  //.w25q64_do_io1    (w25q64_do_io1   ),
  //.w25q64_nwp_io2   (w25q64_nwp_io2  ),
  //.w25q64_nhold_io3 (w25q64_nhold_io3),
  //.w25q64_clk       (w25q64_clk      ),
  //.w25q64_di_io0    (w25q64_di_io0   ),

  //.w25q64_ncs       (w25q64_ncs      ),
  //.w25q64_clk       (w25q64_clk      ),
  //.w25q64_di_io0    (w25q64_di_io0   ),
  //.w25q64_do_io1    (w25q64_do_io1   ),

  .w25q64_ncs       (flash_cs      ),
  .w25q64_clk       (flash_clk      ),
  .w25q64_di_io0    (flash_mosi   ),
  .w25q64_do_io1    (flash_miso   ),

  .ds1302_clk       (ds1302_clk),
  .ds1302_dat       (ds1302_dat),
  .ds1302_rst       (ds1302_rst),
  
  .led_data_read         (led_data_read),
  .led_data_write        (led_data_write),
  .led_ins_read          (led_ins_read),

    .video_hs       (vga_hs),
    .video_vs       (vga_vs),
    .video_de       (video_de),
    .video_rgb      (vga_rgb),

  .cpu_clk_sel (cpu_clk_sel),
  
  .video_busy(video_busy),
  .dummy(dummy)
  
 );




endmodule
